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In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption.
In two levels it can be circuit or logic optimization. Therefore, careful optimization of the adder is of the greatest importance. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.Īdders form an almost obligatory component of every contemporary integrated circuit. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost.
The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. It presents a reversible 5-to-32 decoder, thirty-two reversible buffer registers, and two reversible 32-to-1 multiplexers, too. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors.
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Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. If one of this file is your intelectual property (copyright infringement) or child pornography / immature sounds, please or email to to us.Reversible circuit design can be applied in various emerging technologies such as quantum computing.
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